Intellectual Property

Key Features:


  • No clock domain crossings
  • Fully synchronous design
  • Oversampling (4Links Patent)
  • Only a single clock timing constraint required

RMAP Target:

  • 16MByte address range

Routing Switch:

  • 2 to 32 ports


  • Test-benches with Out-of-Box and Integration tests
  • Supplied as VHDL with simple wrapping into Verilog

FPGA technologies supported by 4Links IP:


  • Spartan®-6
  • Virtex®-7, Kintex®-7
  • Kintex®UltraScale®


  • ProASIC®3
  • RTAX®, RTG®4

Product Briefs

4Links’ SpaceWire IP is based on a version of the CoDec (Coder/Decoder) used in its test equipment for SpaceWire.

Thousands of SpaceWire ports of this test equipment have proved to be interoperable with all the SpaceWire designs to which they have been connected. The IP is flight proven as the fundamental interconnect on a satellite. It also complements the test solutions and cabling on offer by 4Links.


IP Details

  • The IP is implemented in VHDL, but is designed to be instantiated in Verilog with minimal effort.
  • The IP is Supplied as a complete package:
    • Standard, easy to use FIFO-style interface to user logic (Data Flow Channel, DFC)
    • HDL simulation test bench
    • Traffic generator
    • Traffic logger (logging all the received traffic)
  • The simulation test bench enables you to easily see how the IP operates and how to integrate it into your design. A traffic generator (dfc9_master) and logger (dfc9_slave) are included in the test-bench connecting to the 4Links standard Data Flow Channels (used to connect to all 4Links IP). The generator and logger use a simple text based file allowing easy modification and checking of the vectors, so you can customise it to model the actual data in the design.



 IP  Performance  LUTs  BRAM
 CoDec  >200MHz  423  1
 RMAP Target  >150MHz  503  0
 Routing Switch 4port  >150MHz  5528  5
 FDIR  Contact 4Links >>
 Based on Spartan®6 -3 device
 The performance is the FPGA internal clock